module ltacnt
	(clock, resetn, sclr, cnten, load_ltalatch, Q);
input			clock, resetn;
input			sclr, cnten;
input			load_ltalatch;
output	[7:0]	Q;

reg		[7:0]	Q;
wire	[7:0]	Q_ltacnt;

lpm_ltacnt		lpm_ltacnt_inst
				(.clock(clock), .cnt_en(cnten), .sclr(sclr),
				 .aclr(~resetn), .q(Q_ltacnt));
always @(posedge clock or negedge resetn)
begin
	if (!resetn) Q <= 8'b0;
	else if (load_ltalatch) Q <= Q_ltacnt;
end

endmodule

